A trigonometric function computing unit which finds a sine value and a cosine value of numerical data has been known (refer to Patent Document 1). A storage device stores an initial sine value sin θ0 and an initial cosine value cos θ0 as initial numerical values θ0. The trigonometric function computing unit finds the sine value and the cosine value of the input numerical data by the following expressions, from the initial sine value sin θ0 and the initial cosine value cos θ0, which are stored in the storage device, and differences Δθ(Δθ=θ−θ0) between the input numerical data θ and the initial numerical values θ0.sin θ=sin θ0·cos θΔ+cos θ0·sin θΔcos θ=cos θ0·cos θΔ−sin θ0·sin θΔ
Further, there has been known a sine/cosine arithmetic circuit having an absolute value/sign extraction circuit which outputs an absolute value signal of an input phase angle signal and a positive/negative sign signal of the phase angle signal (refer to Patent Document 2). A sine/cosine approximation arithmetic circuit performs an approximation operation of sine operation results and cosine operation results in a predetermined limited quadrant by using a primary approximation operation expression, based on a predetermined less significant bit in the absolute value signal output by the absolute value/sign extraction circuit. According to three significant bits of the positive/negative sign signal and the absolute value signal which are output by the absolute value/sign extraction circuit, a phase rotation processing circuit replaces the sine operation results and the cosine operation results which are output by the sine/cosine approximation arithmetic circuit, and changes signs to thereby output sine operation results and cosine operation results in a quadrant other than the predetermined limited quadrant.
Patent Document 1: Japanese Laid-open Patent Publication No. 11-194926
Patent Document 2: Japanese Laid-open Patent Publication No. 2000-112715
In recent years, performance, especially a bandwidth, of components such as a central processing unit (CPU) constituting an information processing system such as a server and a computer has been greatly improved. Accordingly, in order to improve the total bandwidth of the whole information processing system, it is necessary to increase the speed of a transmission/reception circuit which transmits/receives data to/from the component such as the CPU.
As a method to increase the speed of the transmission/reception circuit, there has been known a method which uses a phase interpolator for the generation of a clock signal of the transmission/reception circuit. Generally, a noise component is superimposed on a data signal that the transmission/reception circuit processes. Here, the use of the phase interpolator for the generation of the clock signal that decides the timing of data processing makes it possible to set the processing timing of the data signal (phase of the clock signal) to an optimum value, and accordingly, can reduce an influence of the noise component superimposed on the data signal.
As a method to increase the speed of the transmission/reception circuit, there has been known a method to increase a frequency of a clock signal of the transmission/reception circuit. However, when a frequency of a square-wave clock signal input to a phase interpolator is increased, phase linearity of the phase interpolator deteriorates. When the frequency of the clock signal is increased, the square-wave clock signal is distorted due to an influence of parasitic capacitance or the like existing in a wiring line in the circuit. When the distorted square-wave clock signal is input to the phase interpolator, phase linearity of the phase interpolator deteriorates.